Resistive Random Access Memory (ReRAM)
AbstractResistive Random-Access Memory (ReRAM) technology has been viewed as one of the most reliable non-volatile memories that have are emerging in markets. In this research paper, the revolution of ReRAM will be analyzed. Also, the paper will also review the recent progress in the technological development of ReRAM. The performance parameters of these non-volatile memories such as their operating voltage, operation speed, resistance ratio, endurance, retention time, device yield, and multilevel storage will be analyzed. Integration and reliability of Re-RAM in the practical level is compared with other types of memories. Challenges faced by users of ReRAM are addressed in regards to technological fallbacks among other challenges. Finally, the future research on the ReRAM will be analyzed.
 S. Mittal, "A Survey of ReRAM-based Architectures for Processing-in-memory and Neural Networks." Machine learning and knowledge extraction 1, no. 1, 2018, p. 75-114.
 S. Sahoo, & S. R. Prabaharan, “Nano-ionic solid state resistive memories (re-RAM): A review”, Journal of nanoscience and nanotechnology, vol.17, no. 1, 2017, p. 72-86.
 H. Akinaga, H. Shima, “ReRAM technology; challenges and prospects”, IEICE Electronics Express. 2012, vol. 9, no. 8, p.795-807.
 H. Shima and Y. Tamai, “Oxide nanolayer improving RRAM operational performance,” Microelectronics Journal, vol. 40, no. 3, 2008, p. 628-632.
 L. Zhao, L. Jiang, Y. Zhang, N. Xiao, & J. Yang, “Constructing fast and energy efficient 1tnr based reram crossbar memory. In 2017 18th International Symposium on Quality Electronic Design (ISQED), IEEE 2017, pp. 58-64.
 Y. Zhang, D. Feng., J. Liu, W. Tong, B. Wu, & C. Fang, “A novel reram-based main memory structure for optimizing access latency and reliability. In 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC), IEEE, pp. 1-6, 2017.
 M. Mao, Y. Cao, S. Yu, & C. Chakrabarti, “Optimizing latency, energy, and reliability of 1T1R ReRAM through appropriate voltage settings. In 2015 33rd IEEE International Conference on Computer Design (ICCD), IEEE, (pp. 359-366). 2015.
 M. A. Lastras-Montaño, A. hofrani, & K. T. Cheng, “A low-power hybrid reconfigurable architecture for resistive random-access memories”. In 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA) (pp. 102-113). 2016.
 M. Shevgoor, N. Muralimanohar, R. Balasubramonian, & Y. Jeon, “Improving memristor memory with sneak current sharing.” In 2015 33rd IEEE International Conference on Computer Design (ICCD) (pp. 549-556, 2015.
 C. Xu, D. Niu, N. Muralimanohar, R. Balasubramonian, T. Zhang, S. Yu, & Y. Xie, “Overcoming the challenges of crossbar resistive memory architectures”, In 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA) IEEE. pp. 476-488, 2015.
 H. H. Li, Y. Chen, C. Liu, J.P. Strachan, & N. Davila, “Looking ahead for resistive memory technology: A broad perspective on reram technology for future storage and computing”, IEEE Consumer Electronics Magazine, vol. 6, no. 1, 2012, pp. 94-103.
 C. Liu, & T. Wu, “ReRAM-based Circuit and System Design for Future Storage and Computing”, In 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) pp. 390-393, 2018.
 H. Shima, F. Takano, H. Muramatsu, H. Akinaga, Y. Tamai, I. H. Inque, and H. Takagi, “Voltage polarity dependent low-power and high-speed resistance switching in CoO resistance random access memory with Ta electrode”, Appl. Phys. Lett. 93, 113504-1 – 113504-3 (2008)
This work is licensed under a Creative Commons Attribution 4.0 International License.